ChipTimer: High Speed Design and Timing Closure

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A New Paradigm

ChipTimer is a design optimization and timing closure tool for high performance designs. It is well known that algorithms and architecture are the most important element of performance, but implementation has a lot of leeway impacting performance. ChipTimer extends the traditional standard cell based design methodology by simultaneous deign and cell library optimization. In order to achieve these goals, it uses novel optimization techniques as well as creates new cells and libraries to implement the design in the most efficient manner. The new cells and libraries are derived from the existing standard cell library originally used to implement the design. It can be used both pre-layout and post-layout stages of the design process. When used at the pre-layout stage, it restructures the design as well as create new cells as may be needed. When used at the post-layout stage, its objective is to preserve timing and replaces the cells on the critical paths with new ones to match the pre-layout timing, and creates the new cells if they don't exist. ChipTimer interfaces to commercial timing analysis and synthesis tools. As such, it can handle any synthesizable design. One can expect about 10% reduction in the number of standard cells, and 30-200% improvement in timing, depending on the design. Naturally, as the clock frequency goes up, so does the power use of the design. The new cells added to the design try to compensate for this as much as feasible.

Inputs to and Outputs from ChipTimer

Inputs to ChipTimer are gate level Verilog netlist, design constraints and standard cell libraries used for implementing the design, and design fails to meet timing requirements as may be reported by timing analysis tools based on the design constraints. It produces a new Verilog netlist, which is usually contains fewer instances of standard cells, a new set of standard cells to be used in the design, spice level netlists for the new standard cells, a new design libraries for these cells based on estimated layout parasitic effects. Layout level implementation of the new cells need to be carried out by the user.

ChipTimer Flow

First we re-characterize and rebuild the libraries using SolutionWare tool set to assure accuracy and completeness. Next ChipTimer restructures the design and analyze the critical paths using commercial tools. It further analyzes the cells on the critical paths, determines the loads they are driving and how fast their inputs are switching. This information is turned into timing constraints for use by CellOpt, which generates a version of the relevant cell to improve the timing of the design. Such cells may be better in some respects compared to the original, and not so good in some other aspects, but they improve the timing of the design. After CellOpt generates a spice level netlist for the new cells, they are characterized by MakeLib over several machines and new design libraries are created. Timing and critical path analysis and new cell generation is repeated until timing closure is achieved, which is typically takes two or three iterations. The number of new cells required naturally depends on the size of the design, but it quickly saturates and levels off around 150-200 new cells. In any case a very small percentage of cells, namely the ones on the critical paths are affected by this process. Turnaround time of each iteration depends on the complexity of flip-flops used in the design, ranging as much as a few days on several fast machines.